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D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 0 0 4
HYB25D512400AT HYB25D512800AT HYB25D512160AT
512Mbit Doubl e Data Rat e SDRAM
DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
The information in this document is subject to change without notice. Edition 2004-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 0 0 4
HYB25D512400AT HYB25D512800AT HYB25D512160AT
512Mbit Doubl e Data Rat e SDRAM
DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYB25D512400AT HYB25D512800AT HYB25D512160AT Revision History: Previous Revision: All Page All Previous Revision: Rev. 1.0 Rev. 0.92 Rev. 0.91 2004-03 2004-02 2003-08
Editorial Changes see Change List Subjects (major changes since last revision) Deleted -5 and -8 speed
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYB25D512[16/40/80]0AT-[6/7/7F]
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 4 4.1 4.2 4.3 4.4 4.5 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD1: Operating Current: One Bank Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 15 15 16 17 17 17 18 21 21 22 30 44 45 50 51 51 52 54 56 62
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Sheet
5
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Overview
1
1.1
* * * * * * * * * * * * * * * * *
Overview
Features
Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst Lengths: 2, 4, or 8 CAS Latency: (1.5), 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8 s Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V 0.2 V (DDR266A, DDR333) VDD = 2.5 V 0.2 V (DDR266, DDR333) P-TSOP66II-1 package Performance -6/-7/-7F -6 Component Module @CL3 @CL2.5 @CL2 DDR333B PC2700-2533 -7 DDR266A PC2100-2033 -- 143 133 -7F DDR266 PC2100-2022 -- 143 133 Unit -- -- MHz MHz MHz
Table 1
Part Number Speed Code Speed Grade max. Clock Frequency
fCK3 fCK2.5 fCK2
166 166 133
1.2
Description
The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 512Mbit Double Data Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration Data Sheet 6 Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Overview of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Table 2 Ordering Information Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) x4 x8 x16 x4 x8 x16 x8 2.0-2-2 DDR266 143 DDR266A 2.5-3-3 166 2.0-3-3 133 DDR333 Package P-TSOP66II-1
Part Number1) HYB25D512400AT-6 HYB25D512800AT-6 HYB25D512160AT-6 HYB25D512400AT-7 HYB25D512800AT-7 HYB25D512160AT-7 HYB25D512800AT-7F
1) HYB: designator for memory components; 25D: DDR SDRAMs at VDDQ = 2.5 V; 512: 512Mbit density; 400/800/160: Product variations x4, x8 and x16: A: Die revision A; T: Package type TSOP; -6/-7/-7F: speed grade - see Table 2
Data Sheet
7
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Pin Configuration
2
Pin Configuration
VDD N.C. VDDQ N.C. DQ0 VSSQ N.C. N.C. VDDQ N.C. DQ1 VSSQ N.C. N.C. VDDQ N.C. N.C. VDD N.C. N.C. WE CAS RAS CS N.C. BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ N.C. DQ1 VSSQ N.C. DQ2 VDDQ N.C. DQ3 VSSQ N.C. N.C. VDDQ N.C. N.C. VDD N.C. N.C. WE CAS RAS CS N.C. BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C. VDDQ LDQS N.C. VDD N.C. LDM WE CAS RAS CS N.C. BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 32Mb x 16 64Mb x 8 128Mb x 4
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C. VSSQ UDQS N.C. VREF VSS UDM CK CK CKE N.C. A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ7 VSSQ N.C. DQ6 VDDQ N.C. DQ5 VSSQ N.C. DQ4 VDDQ N.C. N.C. VSSQ DQS N.C. VREF VSS DM CK CK CKE N.C. A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS N.C. VSSQ N.C. DQ3 VDDQ N.C. N.C. VSSQ N.C. DQ2 VDDQ N.C. N.C. VSSQ DQS N.C. VREF VSS DM CK CK CKE N.C. A12 A11 A9 A8 A7 A6 A5 A4 VSS
Figure 1
Pin Configuration P-TSOP66II-1
Data Sheet
8
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Pin Configuration
Table 3 Symbol CK, CK
Input/Output Functional Description Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for x16 components and control the lower or upper bytes. For x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1) command. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the x16, LDQS corresponds to the data on LDQ[0:7]; UDQS corresponds to the data on UDQ[0:7]. The data strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. No Connect: No internal electrical connection is present. DQ Power Supply: 2.5 V 0.2 V. DQ Ground Power Supply: 2.5 V 0.2 V. Ground SSTL_2 Reference Voltage: (VDDQ /2) 9 Rev. 1.0, 2004-03
CKE
Input
CS
Input
RAS, CAS, WE Input DM Input
BA0, BA1
Input
A0 - A12
Input
DQ
Input/ Output
DQS, (DQS) Input/ LDQS, (LDQS), Output UDQS,(UDQS)
N.C.
- Supply Supply Supply Supply Supply
VDDQ VSSQ VDD VSS VREF
Data Sheet
HYB25D512[16/40/80]0AT-[6/7/7F]
Pin Configuration
DQ0DQ3, DM
DQS
CK, CK
DLL
DQS
Drivers
1 Data
Receivers
1 4 1
DQS Generator
Input Register 1 1
1
4
4
4
COL0
Mask
Data
MUX
2
Write FIFO & Drivers
4
4
8
Read Latch
Bank3 8
8
Bank0 Memory Array (8192 x 2048 x 8)
Sense Amplifier
I/O Gating DM Mask Logic
Bank1
16384
2048 (x8) Column Column Decoder Column Decoder Column Decoder Decoder
Bank2
8
Bank0 Row-Address Latch & Decoder
13
8192
11
Bank Control Logic
Column-Address Counter/Latch 2
13
Row-Address MUX
Refresh Counter
Control Logic
Command Decode
Mode Registers
13
2
15
Address Register
A0 - A12, BA0, BA1 15
CKE CK CK
Figure 2 Note:
Block Diagram 128 Mbit x 4
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Data Sheet
CS WE CAS RAS
10
12
1
COL0
CK, CK
COL0
1
4
4
Rev. 1.0, 2004-03
SPB04304
HYB25D512[16/40/80]0AT-[6/7/7F]
Pin Configuration
DQ0DQ7, DM
DQS
CK, CK
DLL
DQS
Drivers
1 Data
Receivers
1 8 1
DQS Generator
Input Register 1 1
1
8
8
8
COL0
Mask
Data
MUX
Write FIFO & Drivers
8
8
16
2
Read Latch
16 Bank3 16
Bank0 Memory Array (8192 x 1024 x 16)
Sense Amplifier
I/O Gating DM Mask Logic
Bank1
16384
1024 (x16) Column Column Decoder Column Decoder Column Decoder Decoder
Bank2
16
Bank0 Row-Address Latch & Decoder
13
8192
10
Bank Control Logic
Column-Address Counter/Latch 2
13
Row-Address MUX
Refresh Counter
Control Logic
Command Decode
Mode Registers
13
2
15
Address Register
A0 - A12, BA0, BA1 15
CKE CK CK
Figure 3 Note:
Block Diagram 64 Mbit x 8
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Data Sheet
CS WE CAS RAS
11
11
1
COL0
CK, CK
COL0
1
8
8
Rev. 1.0, 2004-03
SPB04305
HYB25D512[16/40/80]0AT-[6/7/7F]
Pin Configuration
LDQS, UDQS
CK, CK
DLL
DQS
Drivers
1 Data
Receivers
16 2 2
DQS Generator
16
Input Register 1 1
16
16
1
COL0
Mask
Data
MUX
Write FIFO & Drivers
16
16
32
2
Read Latch
32 Bank3 32
Bank0 Memory Array (8192 x 512 x 32)
Sense Amplifier
I/O Gating DM Mask Logic
Bank1
16384
512 (x32) Column Column Decoder Column Decoder Column Decoder Decoder
Bank2
32
Bank0 Row-Address Latch & Decoder
13
8192
Bank Control Logic
Column-Address Counter/Latch 2
13
Row-Address MUX
Refresh Counter
Control Logic
Command Decode
Mode Registers
13
2
15
Address Register
A0 - A12, BA0, BA1 15
CKE CK CK
Figure 4 Note:
Block Diagram 32 Mbit x 16
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional DQ, UDQS and LDQS signals. Data Sheet 12 Rev. 1.0, 2004-03
CS WE CAS RAS
10
9
1
COL0
CK, CK
COL0
16
16
1
SPB04306
DQ0DQ15, LDM, UDM
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3
Functional Description
The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mbit Double Data Rate SDRAM is internally configured as a quad-bank DRAM. The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
3.1
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following criteria must be met: No power sequencing is specified during power up or power down given the following criteria: * * * * * *
VDD and VDDQ are driven from a single power converter output VTT meets the specification
A minimum resistance of 42 limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2
or the following relationship must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 s delay prior to applying an executable command. Once the 200 s delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a Precharge ALL command should be applied, placing the device in the "all banks idle" state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
Data Sheet
13
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. MR Mode Register Definition
BA1 0 BA0 0 A12 A11 A10 A9
(BA[1:0] = 00B)
A8 A7 A6 A5 CL w A4 A3 BT w A2 A1 BL w A0
MODE w
reg. addr
Field BL
Bits [2:0]
Type w
1)
Description Burst Length Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1. Note: All other bit combinations are RESERVED. 001 2 010 4 011 8
BT
3
w1)
Burst Type See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2. 0 Sequential 1 Interleaved CAS Latency Number of full clocks from read command to first data valid window; see Chapter 3.2.3. Note: All other bit combinations are RESERVED. 010 011 101 110 2 3 (1.5 Optional, not covered by this data sheet) 2.5
CL
[6:4]
w1)
MODE [12:7] w1)
Operating Mode See Chapter 3.2.4. Note: All other bit combinations are RESERVED. 000000 000010 Normal Operation DLL Reset
1) w = write only register bit
3.2.1
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Data Sheet
14
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.
3.2.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4 Burst Length 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 Notes 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 0 0 1 1 0 0 1 1 Burst Definition Starting Column Address A2 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
3.2.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS latency of 1.5 is an optional feature on this device. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m.(see Figure 5) Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
15
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.2.4
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode (i.e., with A8=0). All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latency = 2, BL = 4
CK CK Command Read NOP CL=2 DQS DQ NOP NOP NOP NOP
CAS Latency = 2.5, BL = 4
CK CK Command Read NOP CL=2.5 DQS DQ NOP NOP NOP NOP
Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 5
Required CAS Latencies
Data Sheet
16
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.3
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
3.3.1
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self refresh operation.
3.3.2
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. I-V curves for the normal and weak drive strength are included in this document. EMR Extended Mode Register Definition
BA1 0 BA0 1 A12 A11 A10 A9
(BA[1:0] = 01B)
A8 A7 A6 A5 A4 A3 A2 A1 DS w A0 DLL w
OPERATING MODE w
reg. addr
Field DLL
Bits 0
Type w
Description DLL Status See Chapter 3.3.1. 0 Enabled 1 Disabled Drive Strength See Chapter 3.3.2, Chapter 4.2 and Chapter 4.3. 0 Normal 1 Weak Operating Mode Note: All other bit combinations are RESERVED. 00000000000 Normal Operation
DS
1
w
MODE
[12:2]
w
Data Sheet
17
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.4
Deselect
Commands
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in Chapter 3.2. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don't care] for x16, [i = 9, j = don't care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care". Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
Data Sheet
18
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was issued at the earliest possible time, as described for each burst type in Chapter 3.5. Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5. Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto Refresh command. The 512Mbit Double Data Rate SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8 s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 7.8 s (70.2 s). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates. Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Data Sheet
19
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description Table 5 Truth Table 1a: Commands CS H L L L L L L L L RAS CAS WE Address X H L H H H L L L X H H L L H H L L X H H H L L L H L X X Bank/Col Bank/Col X Code X Op-Code MNE NOP NOP Read Write BST PRE AR/SR MRS Notes
1)2) 1)2) 1)3) 1)4) 1)4) 1)5) 1)6) 1)7)8) 1)9)
Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set
1) CKE is HIGH for all commands shown except Self Refresh. 2) Deselect and NOP are functionally interchangeable.
Bank/Row ACT
3) BA0-BA1 provide bank address and A0-A12 provide row address. 4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. 5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts. 6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". 7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW. 8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register).
Table 6
Truth Table 1b: DM Operation DM L H DQs Valid X Notes
1) 1)
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
Data Sheet
20
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.5 3.5.1
Operations Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Figure 6), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.
CK CK CKE CS RAS CAS WE A0-A12 BA0, BA1 RA BA RA = row address. BA = bank address. Don't Care HIGH
Figure 6
Activating a Specific Row in a Specific Bank
CK CK Command A0-A12 BA0, BA1
ACT ROW BA x NOP ACT ROW BA y NOP NOP RD/WR COL BA y NOP NOP
tRRD
tRCD
Don't Care
Figure 7
tRCD and tRRD Definition
Data Sheet
21
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.5.2
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on Figure 8. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). Figure 9 shows general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 10. A Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read data is illustrated on Figure 11. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on Figure 12.
CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
CA EN AP
Figure 8
Read Command
Data Sheet
22
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command Address
Read
BA a,COL n
NOP
NOP
NOP
NOP
NOP
CL=2 DQS DQ
DOa-n
CAS Latency = 2.5
CK CK Command Address
Read BA a,COL n NOP NOP NOP NOP NOP
CL=2.5 DQS DQ
DOa-n
DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 9
Read Burst: CAS Latencies (Burst Length = 4)
Data Sheet
23
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command Address
Read NOP Read NOP NOP NOP
BAa, COL n
BAa, COL b
CL=2 DQS DQ
DOa-n DOa-b
CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
Read
BAa,COL b
NOP
NOP
NOP
CL=2.5 DQS DQ
DOa- n DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 10
Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
24
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
NOP
NOP
Read
BAa, COL b
NOP
NOP
CL=2 DQS DQ
DO a-n DOa- b
CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
NOP
Read
BAa, COL b
NOP
NOP
NOP
CL=2.5 DQS DQ
DO a-n DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b). Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 11
Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Data Sheet
25
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
Read
BAa, COL x
Read
BAa, COL b
Read
BAa, COL g
NOP
NOP
CL=2 DQS DQ
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b' DOa-g
CAS Latency = 2.5
CK CK Command Address
Read Read Read Read NOP NOP
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
CL=2.5 DQS DQ
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b'
DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 12
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 13. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown on Figure 14. The example is shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are defined in Chapter 3.5.3. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 15 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements. Data Sheet 26 Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2 DQS DQ
DOa-n
No further output data after this point. DQS tristated. CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2.5 DQS DQ
DOa-n
No further output data after this point. DQS tristated.
DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 13
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
Data Sheet
27
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command Address
Read BST NOP Write NOP NOP
BAa, COL n
BAa, COL b
CL=2 DQS DQ DM
DOa-n
tDQSS (min)
DI a-b
CAS Latency = 2.5
CK CK Command Address
Read BST NOP NOP Write NOP
BAa, COL n
BAa, COL b
CL=2.5 DQS DQ DM
DOa-n
tDQSS (min)
Dla-b
DO a-n = data out from bank a, column n . a-b = data in to bank a, column b DI 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 14
Read to Write: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
28
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CAS Latency = 2
CK CK Command
Read NOP PRE NOP NOP ACT
tRP Address
BA a, COL n BA a or all BA a, ROW
CL=2 DQS DQ
DOa-n
CAS Latency = 2.5
CK CK Command
Read NOP PRE NOP NOP ACT
tRP Address
BA a, COL n BA a or all BA a, ROW
CL=2.5 DQS DQ
DOa-n
DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
Figure 15
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
29
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.5.3
Writes
Write bursts are initiated with a Write command, as shown in Figure 16. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Figure 17 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 18 shows concatenated bursts of 4. An example of non-consecutive Writes is shown in Figure 19. Full-speed random write accesses within a page or pages can be performed as shown in Figure 20. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown in Figure 21. Data for any Write burst may be truncated by a subsequent Read command, as shown in Figure 22 to Figure 24. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, tWR should be met as shown in Figure 25. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in Figure 26 to Figure 28. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
Data Sheet
30
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
CA EN AP
Figure 16
Write Command
Data Sheet
31
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command Address
Write
BA a, COL b
T2
T3
T4
NOP
NOP
NOP
tDQSS (max) DQS DQ DM
Dla-b
Minimum DQSS
T1 CK CK Command Address
Write BA a, COL b NOP NOP NOP
T2
T3
T4
tDQSS (min) DQS DQ DM
Dla-b
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled).
Don't Care
Figure 17
Write Burst (Burst Length = 4)
Data Sheet
32
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command Address
Write NOP Write NOP NOP NOP
T2
T3
T4
T5
T6
BAa, COL b
BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b DI a-n
Minimum DQSS
T1 CK CK Command Address
Write
BA, COL b
T2
T3
T4
T5
T6
NOP
Write
BA, COL n
NOP
NOP
NOP
tDQSS (min) DQS DQ DM
DI a-b DI a-n
DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.
Don't Care
Figure 18
Write to Write (Burst Length = 4)
Data Sheet
33
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
T1 CK CK Command Address
Write
T2
T3
T4
T5
NOP
NOP
Write
NOP
BAa, COL b
BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b DI a-n
DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.
Don't Care
Figure 19
Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)
Data Sheet
34
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command Address
Write
BAa, COL b
T2
T3
T4
T5
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
tDQSS (max) DQS DQ DM
DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a'
Minimum DQSS
T1 CK CK Command Address
Write
BAa, COL b
T2
T3
T4
T5
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
tDQSS (min) DQS DQ DM
DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' DI a-g
DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank.
Don't Care
Figure 20
Random Write Cycles (Burst Length = 2, 4 or 8)
Data Sheet
35
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b
CL = 2
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWTR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank.
Don't Care
Figure 21
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Data Sheet
36
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (max) DQS DQ DM
DIa- b
CL = 2
1
1
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Figure 22
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Data Sheet
37
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
NOP
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
1
2
2
DI a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element) The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = This bit is correctly written into the memory array if DM is low. Don't Care 2 = These bits are incorrectly written into the memory array if DM is low.
Figure 23
Write to Read: Minimum DQSS, Odd Number of Data (3-bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)
Data Sheet
38
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
NOP
tWTR Address
BAa, COL b BAa, COL n
tDQSS (nom) DQS DQ DM
DI a-b
CL = 2
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Figure 24
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
Data Sheet
39
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP NOP PRE
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (max) DQS DQ DM
DI a-b
tRP
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP NOP PRE
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
tRP
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled).
Don't Care
Figure 25
Write to Precharge: Non-Interrupting (Burst Length = 4)
Data Sheet
40
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP PRE NOP
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (max) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP PRE NOP
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Figure 26
Write to Precharge: Interrupting (Burst Length = 4 or 8)
Data Sheet
41
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
NOP
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
2
tRP
3
4
4
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Figure 27
Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst Length = 4 or 8)
Data Sheet
42
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
NOP
tWR Address
BA a, COL b BA (a or all)
tDQSS (nom) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Figure 28
Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)
Data Sheet
43
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.5.4
Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care". Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank.
CK CK CKE CS RAS CAS WE A0-A9, A11, A12 All Banks A10 BA0, BA1 One Bank BA BA = bank address (if A10 is Low, otherwise Don't Care). Don't Care HIGH
Figure 29
Precharge Command
Data Sheet
44
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.5.5
Power-Down
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down mode. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect command). A valid, executable command may be applied one clock cycle later.
CK CK CKE tIS tIS
Command
VALID No column access in progress
NOP
NOP Exit power down mode
VALID
Enter Power Down mode (Burst Read or Write operation must not be in progress)
Don't Care
Figure 30
Power Down
Data Sheet
45
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description Table 7 Truth Table 2: Clock Enable (CKE) CKEn Current Cycle L H L H L L L H X Deselect or NOP X Deselect or NOP Deselect or NOP AUTO REFRESH Deselect or NOP See Table 8 Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Self Refresh Entry Active Power-Down Entry - -
1)
Current State CKE n-1 Previous Cycle Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle L L L L H H H
Command n
Action n
Notes
- - - - -
Precharge Power-Down Entry -
Bank(s) Active H
1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1. 2. 3. 4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. Truth Table 3: Current State Bank n - Command to Bank n (same bank) RAS CAS WE X H L L L H H L H L H H H L X H H L L L L H L H H L L H X H H H L H L L H L L H L L Command Deselect No Operation Active AUTO REFRESH MODE REGISTER SET Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. Select and activate row - - Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column and start Read burst Select column and start Write burst Truncate Write burst, start Precharge Notes
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 7) 1) to 7)
Table 8 Any Idle
Current State CS H L L L L Row Active L L L Read (Auto Precharge Disabled) L L L Write (Auto Precharge Disabled) L L L
1) to 6), 8) 1) to 6), 8) 1) to 6), 9) 1) to 6), 8)
1) to 6), 9)
1) to 6), 10)
1) to 6), 8), 11) 1) to 6), 8) 1) to 6), 9), 11)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7 and after tXSNR/tXSRD has been met (if the previous state was self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
Data Sheet
46
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 9. 5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 11) Requires appropriate DM masking.
Data Sheet
47
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description Table 9 Any Idle Truth Table 4: Current State Bank n - Command to Bank m (different bank) CS H L X RAS CAS WE X H X X H X X H X Command Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. - Notes
1)2)3)4)5)6) 1) to 6) 1) to 6)
Current State
Row Activating, Active, or Precharging
L L L L L L L
L H H L L H L L H H L L H H L L H H L
H L L H H L H H L L H H L L H H L L H
H H L L H H L H H L L H H L L H H L L
Select and activate row Select column and start Read burst Select column and start Write burst - Select and activate row Select column and start new Read burst - Select and activate row Select column and start Read burst Select column and start new Write burst - Select and activate row Select column and start new Read burst Select column and start Write burst - Select and activate row Select column and start Read burst Select column and start new Write burst -
1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7)
Read (Auto Precharge Disabled)
1) to 6) 1) to 6) 1) to 8) 1) to 7)
Write (Auto Precharge Disabled)
L L L L
1) to 6) 1) to 6) 1) to 7), 9)
Read (With Auto L Precharge) L L L Write (With Auto L Precharge) L L L
1) to 7), 9), 10) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7), 9)
1) to 6)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if the previous state was self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See 10). Write with Auto Precharge Enabled: See 10). 4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved.
Data Sheet
48
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking. 9) Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 10. 10) A Write command may be applied after the completion of data output.
Table 10
Truth Table 5: Concurrent Auto Precharge To Command (different bank) Read or Read w/AP Write to Write w/AP Precharge or Activate Minimum Delay with Concurrent Auto Precharge Support 1 + (BL/2) + tWTR BL/2 1 BL/2 CL (rounded up) + BL/2 1 Unit
From Command WRITE w/AP
Read w/AP
Read or Read w/AP Write or Write w/AP Precharge or Activate
tCK tCK tCK tCK tCK tCK
Data Sheet
49
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Functional Description
3.6
Simplified State Diagram
Power Applied
Power On
Precharge PREALL
Self Refresh REFS REFSX
MRS EMRS
MRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
ACT
Precharge Power Down
Write Write A Write
Row Active
Burst Stop Read
Read A Read Read
Write A Read A Write A PRE PRE PRE
Read A
Read A
PRE
Precharge PREALL Automatic Sequence Command Sequence
PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh
CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge
Figure 31
Simplified State Diagram
Data Sheet
50
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
4
4.1
Table 11 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values min. typ. max. -0.5 -- -1.0 -- -1.0 -- -1.0 -- 0 -55 -- -- -- -- 1.5 50 Unit Note/ Test Condition -- -- -- -- -- -- -- --
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ+0.5 V
+3.6 +3.6 +3.6 +70 +150 -- -- V V V C C W mA
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
Table 12 Parameter
Input and Output Capacitances Symbol Min. Values Typ. -- -- -- -- -- -- Max. 2.5 0.25 3.0 0.5 5.0 0.5 pF pF pF pF pF pF 1.5 -- 2.0 -- 4.0 -- Unit Note/ Test Condition TSOPII 1)
1)
Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM
CI1 CdI1 CI2 CdIO CIO CdIO
TSOPII 1)
1)
TSOPII 1)2)
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 100 MHz, TA = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground. 2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
Data Sheet
51
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
4.2
Normal Strength Pull-down and Pull-up Characteristics
1. The nominal pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 2. The full variation in driver pull-down current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 3. The nominal pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 4. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 5. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 V.
140 120
Maximum
IOUT (mA)
100 80 60 40 20 0 0 0.5 1 1.5 2 2.5
Nominal High Nominal Low Minimum
VDDQ - VOUT (V)
Figure 32 Normal Strength Pull-down Characteristics 0 -20 -40 Minimum Nominal Low
IOUT (mA)
-60 -80 -100 -120 -140 -160
Nominal High Maximum 0 0.5 1
VDDQ - VOUT (V)
1.5
2
2.5
Figure 33
Normal Strength Pull-up Characteristics
Data Sheet
52
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics Table 13 Voltage (V) Nominal Low 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Table 14 Parameter Operating Temperature 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Normal Strength Pull-down and Pull-up Currents Pulldown Current (mA) Nominal High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 min. 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 max. 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Nominal Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Nominal High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 min. -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 max. -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Pull-down and Pull-up Process Variations and Conditions Nominal 25 C 2.5 V Minimum 0 C 2.3 V Maximum 70 C 2.7 V
VDD/VDDQ
Data Sheet
53
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
4.3
Weak Strength Pull-down and Pull-up Characteristics
1. The weak pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 2. The weak pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 3. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 4. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 V.
80 70 60
Maximum Typical high Typical low Minimum
Iout [mA]
50 40 30 20 10 0 0,0 0,5 1,0 1,5 2,0
2,5
Vout [V]
Figure 34
Weak Strength Pull-down Characteristics
0,0 0,0 -10,0 -20,0 -30,0
Minimum
0,5
1,0
1,5
2,0
2,5
Iout [V]
Typical low
-40,0 -50,0 -60,0 -70,0 -80,0
Typical high
Maximum
Vout [V]
Figure 35
Weak Strength Pull-up Characteristics
Data Sheet
54
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
Table 15 Voltage (V)
Weak Strength Driver Pull-down and Pull-up Characteristics Pulldown Current (mA) Nominal Low Nominal High 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 min. 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 max. 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 Nominal Low -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 Pullup Current (mA) Nominal High -4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 min. -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 max. -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
3.4 6.9 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8
Data Sheet
55
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
4.4
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 36 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level). 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification for DDR components.
VTT
50 Output (VOUT) Timing Reference Point
30 pF
Figure 36
AC Output Load Circuit Diagram / Timing Reference Load
Data Sheet
56
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics Table 16 Parameter AC Operating Conditions1) Symbol min. Input High (Logic 1) Voltage, DQ, DQS and VIH(AC) DM Signals Input Low (Logic 0) Voltage, DQ, DQS and VIL(AC) DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs
2) Input slew rate = 1 V/ns. 3) Inputs are not recognized as valid until VREF stabilizes. 4) VID is the magnitude of the difference between the input level on CK and the input level on CK. 5) The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.
Values max. -
Unit V V V V
Note/ Test Condition
2)3)
VREF + 0.31
- 0.7 0.5 x VDDQ - 0.2
VREF - 0.31 VDDQ + 0.6
0.5 x VDDQ + 0.2
2)3)
VID(AC) VIX(AC)
2)3)4)
2)3)5)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V
Table 17 Parameter
AC Timing - Absolute Specifications DDR333, DDR266A and DDR266 TSOP Symbol Min. -6 DDR333 Max. +0.7 +0.6 0.55 0.55 -- 12 12 -- -- -- -- +0.7 +0.7 1.25 7.5 7.5 0.5 0.5 2.2 1.75 12 12 -- -- -- -- 7.5 7.5 0.5 0.5 2.2 1.75 12 12 -- -- -- -- ns ns ns ns ns ns ns ns CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5)
-7 DDR266A Min. Max. -0.75 +0.75 -0.75 +0.75 0.45 0.45 0.55 0.55 Min.
-7F DDR266 Max. -0.75 +0.75 -0.75 +0.75 0.45 0.45 0.55 0.55
Unit Note/ Test Condition 1)
2)3)4)5)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK3 tCK2.5 tCK2 tDH tDS tIPW tDIPW
-0.7 -0.6 0.45 0.45 -- 6.0 7.5 0.45 0.45 2.2 1.75 -0.7 -0.7 0.75
ns ns
2)3)4)5)
tCK tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
Data-out high-impedance tHZ time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition
-0.75 -- -0.75 +0.75 0.75 1.25
-0.75 +0.75 -0.75 +0.75 0.75 1.25
2)3)4)5)7)
tLZ tDQSS
2)3)4)5)7)
tCK
2)3)4)5)
Data Sheet
57
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics Table 17 Parameter AC Timing - Absolute Specifications DDR333, DDR266A and DDR266 TSOP Symbol Min. DQS-DQ skew (DQS and tDQSQ associated DQ signals) -- -- 0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8 Address and control input tIH hold time 0.75 0.8 Read preamble Read postamble Active to Precharge command Active to Active/Autorefresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Data Sheet -6 DDR333 Max. +0.45 +0.55 -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 70E+3 -- -- -- -- 0.35 0.2 0.2 2 0 0.40 0.25 0.9 1.0 0.9 1.0 0.9 0.40 45 65 75 Min. -7 DDR266A Max. +0.5 +0.75 -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 -- -- 0.35 0.2 0.2 2 0 0.40 0.25 0.9 1.0 0.9 1.0 0.9 0.40 Min. -7F DDR266 Max. +0.5 +0.75 -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 ns ns ns TSOP2)3)4)5) TSOP2)3)4)5)
2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
tQHS DQ/DQS output hold time tQH DQS input low (high) pulse tDQSL,H
Data hold skew factor width (write cycle) DQS falling edge to CK setup time (write cycle)
tHP -tQHS
tHP - tQHS
tHP -tQHS
tCK tCK tCK tCK
ns
tDSS
2)3)4)5)
DQS falling edge hold time tDSH from CK (write cycle) Mode register set command cycle time Write postamble
2)3)4)5)
tMRD
2)3)4)5)
Write preamble setup time tWPRES
2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPST Write preamble tWPRE Address and control input tIS
setup time
tCK tCK
ns ns ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE tRPST tRAS tRC tRFC
0.9 0.40 42 60 72
tCK tCK
120E+3 45 -- -- 65 75
120E+3 ns -- -- ns ns
2)3)4)5)
2)3)4)5)
tRCD tRP tRAP tRRD tWR tDAL
18 18
-- --
20 20
-- --
20 20
-- --
ns ns ns ns ns
2)3)4)5)
2)3)4)5)
tRCD or tRASmin 12 15 -- --
tRCD or tRASmin 15 15 -- --
tRCD or tRASmin 15 15 -- --
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)11)
(tWR/tCK) + (tRP/tCK)
tCK
58
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics Table 17 Parameter AC Timing - Absolute Specifications DDR333, DDR266A and DDR266 TSOP Symbol Min. Internal write to read command delay Exit self-refresh to nonread command Exit self-refresh to read command -6 DDR333 Max. -- -- -- 7.8 Min. 1 75 200 -- -7 DDR266A Max. -- -- -- 7.8 1 75 200 -- Min. -7F DDR266 Max. -- -- -- 7.8 Unit Note/ Test Condition 1)
tWTR tXSNR tXSRD
1 75 200 --
tCK
ns
2)3)4)5)
2)3)4)5)
tCK
s
2)3)4)5)
Average Periodic Refresh tREFI Interval
2)3)4)5)12)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR266A 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
59
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
Table 18 Parameter
IDD Conditions
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK =
IDD0
IDD1 IDD2P
tCKMIN
Precharge Floating Standby Current: CS VIHMIN, all banks idle; IDD2F CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD2Q
IDD3P
Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, IDD3N DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs IDD4R changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs IDD4W changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN Auto-Refresh Current: tRC = tRFCMIN, burst refresh Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test conditions.
IDD5 IDD6 IDD7
Data Sheet
60
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
Table 19 Symbol
IDD Specification and Conditions
-6 DDR333 typ. max. 200 200 215 215 18 60 40 23 75 75 245 245 235 130 335 5 405 405 typ. 135 135 145 145 10 40 20 14 55 55 165 165 160 90 255 2.5 315 315 -7 DDR266A max. 170 170 180 180 14 50 28 18 70 70 200 200 195 105 310 5 380 380 147 140 158 151 10 40 20 14 55 55 172 172 166 94 270 2.5 331 343 typ. -7F DDR266 max. 185 177 196 187 14 50 28 18 70 70 208 208 203 109 329 5 399 414 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x8 2)3) x16 3) x4/x8 3) x16 3)
3) 3) 3) 3)
Unit
Note/Test Condition1)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
155 155 170 170 12 45 30 17 60 60 200 200 190 110 270 2.5 330 330
x4/x8 3) x16 3) x4/x8 3) x16 3) x4/x8 3) x16 3)
3)4)
x4/x8 3) x4/x8 3) x16 3)
1) Test conditions for typical values: VDD = 2.5 V (DDR266, DDR333), TA = 25 C, test conditions for maximum values: VDD = 2.7 V, TA = 10 C 2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333. 3) Input slew rate = 1 V/ns. 4) Enables on-chip refresh and address counters.
Data Sheet
61
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Electrical Characteristics
4.5
IDD1: Operating Current: One Bank Operation
1. Only one bank is accessed with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0 mA. 2. Timing patterns a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRCD = 2 x tCK, tRAS = 5 x tCK Setup: A0 N R0 N N P0 N Read: A0 N R0 N N P0 N - repeat the same timing with random address changing 50% of data changing at every burst b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRCD = 3 x tCK, tRC = 9 x tCK, tRAS = 5 x tCK Setup: A0 N N R0 N P0 N N N Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing 50% of data changing at every burst c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRCD = 3 x tCK, tRC = 9 x tCK, tRAS = 5 x tCK Setup: A0 N N R0 N P0 N N N Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing 50% of data changing at every burst 3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
IDD7: Operating Current: Four Bank Operation 1. Four banks are being interleaved with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are not changing. IOUT = 0 mA.
2. Timing patterns a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK, Read with autoprecharge Setup: A0 N A1 R0 A2 R1 A3 R2 Read: A0 R3 A1 R0 A2 R1 A3 R2 - repeat the same timing with random address changing 50% of data changing at every burst b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst 3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
Data Sheet
62
Rev. 1.0, 2004-03
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
5
Timing Diagrams
tDQSL tDQSH DQS tDH tDS DQ
DI n
tDH tDS DM
DI n = Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n.
Don't Care
Figure 37
Data Input (Write), Timing Burst Length = 4
DQS tDQSQ max tQH
DQ
tQH (Data output hold time from DQS) tDQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration. .DQSQ and tQH both apply to each of the four relevant edges of DQS. t tDQSQ max. is used to determine the worst case setup time for controller data capture. tQH is used to determine the worst case hold time for controller data capture.
Figure 38
Data Output (Read), Timing Burst Length = 4
Data Sheet
63
Rev. 1.0, 2004-03
Figure 39
Data Sheet
* VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latchup. ** tMRD is required before any command can be applied and 200 cycles of CK are required before a Read command can be applied. The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All command.
tVTD tCK tCH
VDD
VDDQ
VTT (System*)
VREF
200 cycles of CK**
tCL tMRD tMRD tRP tRFC tRFC tMRD
200s
CK CK
tIH tIS
Initialize and Mode Register Sets
tIH tIS NOP PRE EMRS MRS PRE AR AR MRS ACT
CKE
LVCMOS LOW LEVEL
Command
64
tIH tIS CODE tIH tIS CODE tIS CODE tIH tIS CODE tIH
DM
A0-A9, A11
CODE
RA
A10
ALL BANKS
tIH tIS BA0=H BA1=L
CODE
RA
ALL BANKS
BA0, BA1
BA0=L BA1=L
BA0=L BA1=L
BA
High-Z
DQS
High-Z
DQ
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
Power-up: VDD and CK stable
Don't Care
Extended Mode Register Set
Load Mode Register, Reset DLL
Load Mode Register (with A8 = L)
Figure 40
Data Sheet
tCK tCH tCL tIH tIS tIS tIS tIH tIS VALID* NOP tIH tIS VALID VALID NOP VALID
Enter Power Down Mode
CK
CK
Power Down Mode
CKE
Command
ADDR
65
DQS
DQ
DM
Exit Power Down Mode
HYB25D512[16/40/80]0AT-[6/7/7F]
No column accesses are allowed to be in progress at the time power down is entered. * = If this command is a Precharge (or if the device is already in the idle state) then the power down mode shown is Precharge power down. If this command is an Active (or if at least one row is already active), then the power down mode shown is Active power down.
Don't Care
Timing Diagrams
Rev. 1.0, 2004-03
Figure 41
tRP tCH tCK tRFC tRFC tCL
Data Sheet
VALID VALID PRE NOP NOP AR NOP AR NOP NOP ACT RA RA
CK CK
tIH
tIS
Auto Refresh Mode
ALL BANKS
RA
CKE
tIH
tIS
Command
NOP
A0-A8
A9, A11,A12
66
ONE BANK
tIH tIS BANK(S)
A10
BA0, BA1
BA
DQS
DQ
DM
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
Don't Care
Figure 42
Data Sheet
Clock must be stable before exiting Self Refresh Mode
tRP* tCK tCH tCL
200 cycles
Self Refresh Mode
tIH tIS tIS tIS tIH tIS NOP AR NOP tXSRD, tXSRN VALID tIH tIS VALID
CK CK
CKE
Command
67
Enter Self Refresh Mode Exit Self Refresh Mode
ADDR
DQS
DQ
DM
HYB25D512[16/40/80]0AT-[6/7/7F]
* = Device must be in the all banks idle state before entering Self Refresh Mode. ** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK). are required before a Read command can be applied.
Timing Diagrams
Rev. 1.0, 2004-03
Don't Care
tCK tCH tRP
Figure 43
tCL
Data Sheet
tIH tIS VALID tIH tIS NOP tIH tIS Read NOP PRE NOP NOP ACT NOP NOP NOP VALID VALID tIH
CK CK
CKE
Command
A0-A9, A11, A12
COL n
RA tIH tIS
ALL BANKS
RA
A10
DIS AP ONE BANK
tIH tIS BA x BA x* BA x
BA0, BA1
Read without Auto Precharge (Burst Length = 4)
68
tLZ (min) tRPRE tAC (min) tHZ (min) tRPST tDQSCK (min)
DM
DQS
Case 1: tAC/tDQSCK = min
CL=2 DO n
tLZ (max) tRPRE
DQ
DQS
tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max
DQ
DO n
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
Don't Care
DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
NOP commands are shown for ease of illustration; other commands may be valid at these times.
tCK tCH tRP
Figure 44
tCL
Data Sheet
tIH tIS VALID tIH tIS VALID VALID tIH
CK CK
CKE
Command
tIH tIS COL n tIH tIS RA RA
NOP
Read NOP NOP NOP NOP ACT NOP NOP NOP
A0-A9, A11, A12
A10
EN AP
tIH tIS BA x BA x
BA0, BA1
Read with Auto Precharge (Burst Length = 4)
69
tLZ (min) tRPRE tLZ (min) tAC (min) tRPST tDQSCK (min) tHZ (min)
DM
DQS
Case 1: tAC/tDQSCK = min
CL=2 DO n
tLZ (max) tRPRE
DQ
DQS
tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max
DQ
DO n
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. EN AP = enable Auto Precharge. ACT = active; RA = row address. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Don't Care
tCK
tCL tCH
Figure 45
Data Sheet
CK CK
tIH tIS VALID tIH tIS NOP NOP Read NOP PRE NOP NOP ACT NOP tIH tIS RA COL n tIH tIS ALL BANKS RA ONE BANK RA ACT tRC
CKE
Command
A0-A9, A11, A12
A10
DIS AP
tIH tIS BA x BA x BA x*
Bank Read Access (Burst Length = 4)
RA
BA x
BA0, BA1 DM
tLZ (min) tRPRE
70
tRCD tRAS tLZ (min) tAC (min)
tRP
DQS
tHZ (min) tRPST tDQSCK (min)
Case 1: tAC/tDQSCK = min
CL=2
DQ
DO n
tLZ (max) tRPRE
DQS
tHZ (max) tAC (max) tLZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max DQ
DO n
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. DIS AP = disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Don't Care
tCH tCK tCL tRP tWR
Figure 46
Data Sheet
tIH tIH VALID tIH Write NOP NOP NOP NOP PRE NOP NOP ACT tIH tIS COL n RA tIH tIS
CK
CK
tIS
CKE
tIS
Command
NOP
A0-A9, A11, A12
ALL BANKS
RA
A10 ONE BANK
tIH tIS BA x tWPRE tWPRES tDQSH tDQSS tWPST tDQSL tDSH BA x*
DIS AP
Write without Auto Precharge (Burst Length = 4)
71
DIn
BA0, BA1
BA
DQS
DQ
DM
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
tDQSS = min. DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
Don't Care
tCH tCK tCL tRP tWR
Figure 47
Data Sheet
tIH tDAL VALID VALID VALID tIH Write NOP NOP NOP NOP NOP NOP NOP ACT tIH tIS COL n tIH tIS RA
CK
CK
tIS
CKE
tIS
Command
NOP
A0-A9, A11, A12
A10
tIH tIS BA x
EN AP
RA
Write with Auto Precharge (Burst Length = 4)
72
tWPRES tDQSS tWPST tDQSH tDQSL tDSH DIn tWPRE
BA0, BA1
BA
DQS
DQ
DM
tDQSS = min.
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. EN AP = Enable Auto Precharge. ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
Don't Care
Figure 48
tCH tCK tCL
Data Sheet
tIH VALID tIH tRAS ACT NOP Write NOP NOP NOP NOP PRE NOP tIH tIS RA Col n tIH tIS RA
CK
CK
tIS
CKE
tIS
Command
NOP
A0-A9, A11, A12
Bank Write Access (Burst Length = 4)
ALL BANKS ONE BANK
tIH tIS BA x BA x tRCD tWPRES tDQSH tDQSS tDQSL tWPST tDSH tWR BA x
A10
DIS AP
73
DIn tWPRE
BA0, BA1
DQS
DQ
DM
HYB25D512[16/40/80]0AT-[6/7/7F]
tDQSS = min. DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n. DIS AP = Disable Auto Precharge. * = don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
Timing Diagrams
Rev. 1.0, 2004-03
Don't Care
tCH tCK tCL
Figure 49
Data Sheet
tIH VALID tIH Write NOP NOP NOP NOP PRE NOP NOP ACT tIH tIS COL n RA tIH tIS
CK
CK
tIS
CKE
tIS
Command
NOP
A0-A9, A11, A12
ALL BANKS
RA
Write DM Operation (Burst Length = 4)
DIS AP ONE BANK
tIH tIS BA x BA x* BA
A10
74
tWPRES tDQSH tDQSS tDQSL tWPST tDSH tWR DIn
BA0, BA1
tRP
DQS
DQ
DM
HYB25D512[16/40/80]0AT-[6/7/7F]
Timing Diagrams
Rev. 1.0, 2004-03
DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked). DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. tDQSS = min.
Don't Care
HYB25D512[16/40/80]0AT-[6/7/7F]
Package Outlines
6
Package Outlines
1 0.05
15 5
0.1 0.05
10.16 0.13 2)
0.65 15 5 32 x 0.65 = 20.8 0.3 0.08
3)
0.5 0.1 11.76 0.2
0.1 66x 0.12
M
66x
66
34
6 MAX.
1 2.5 MAX. 22.22 0.13 1) Index Marking
33
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include plastic protrusion of 0.25 max. per side 3) Does not include dambar protrusion of 0.13 max.
Figure 50 P-TSOP66II-1 (Plastic Thin Small Outline Package Type II)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 75 Dimensions in mm Rev. 1.0, 2004-03
0.15 +0.06 -0.03
0.25
www.infineon.com
Published by Infineon Technologies AG

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